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Utsav H. Bhatt ¹, Ekata Mehul ¹, Anurag P. Lakhlani ¹, Amit  Kumar ¹

Affiliations
1 Department of Electronics and Communication, MEF Group of Institutions, Rajkot-360003, IN

Abstract

The paper present various possible jitter reduction technique while designing a Phase Locked Loop. Basic block which makes Phase Locked Loop are Phase detector, Loop Filter and Voltage Control Oscillator including suitable feedback. While reducing the jitter of PLL at the output, reduction in bandwidth of loop filter reducing the gain of phase detector, reducing the gain of the VCO, modifying basic building block and several other technique is proposed.

Keywords

Phase Locked Loop (PLL), Phase Frequency Detector (PFD), Charge-Pump (CP), Current Starved Voltage Control Oscillator (CSVCO).

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Utsav H. Bhatt ¹, Anurag P. Lakhlani ¹, Amit Kumar ¹

Affiliations
1 Department of Electronics and Communication, MEF Group of Institutions, Rajkot-360003, IN

Abstract

The paper presents a designing a low jitter Phase Locked Loop (PLL). To reduce the jitter design is modified such that it gives minimal phase variation at the output of voltage controlled oscillator. The design uses phase frequency detector with charge pump configuration. The current source output of charge pump given to the current starved voltage controlled oscillator. The VCO is design of 100 Mhz with 50 nm technology BSIM4 model used for simulation in LTSpice. The design has advantage in lower area as well as faster acquisition time of PLL.

Keywords

Phase Locked Loop (PLL), Phase Frequency Detector (PFD), Charge-Pump (CP), Current Starved Voltage Control Oscillator (CSVCO).

Full Text